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iW-Video Switch
• LCD Interfacing
• Camera Interfacing
• Video Decoder Interfacing
• Video Encoder Interfacing
• Chroma Resampling
• Color Space Conversion
• Video Scaling
• Deinterlacing
• SDRAM Controller
The example design employs all cores described above although each one is designed to be able to be used as a stand-alone unit (for more information on the cores, see the section core descriptions).
In the example design, video is input from a digital camera or video decoder as selected, and processed by the iWave IP cores inside the FPGA according to the requirements of the output device. The output device can be an LCD or video encoder as selected by the user.
Thus, the following video streaming implementations are possible using the example design: digital camera to LCD, Video Decoder to LCD or Video Decoder to Video Encoder.
Functional Description
All modules shown (except write/read DMA functions) are part of the iWave Video IP library. Video data with associated synchronization signals is input into the design through either of the digital camera or video decoder interfaces and after processing, is output to the LCD or video decoder interfaces.
When streaming to the LCD, if the input video from the camera/decoder is not progressively scanned, a deinterlacer performs the conversion from interlaced to progressive. Since the LCD also expects RGB formatted pixels, a color space converter converts them from Y´CbCr to RGB format.
Functions performed by various modules in the design are described below.
Camera Interface: This block accepts synchronized Y´CbCr 4:2:2 / RGB x:x:x input from a digital camera (or image sensor).
Video Decoder Interface: This block accepts synchronized Y´CbCr 4:2:2 NTSC/PAL input (as per recommendation 601/656) from a video decoder like ADV 7180.
Chroma resampler: This block upsamples or downsamples the chrominance components of images e.g. from Y´CbCr 4:2:2 to 4:4:4 (upsampling) or Y´CbCr 4:4:4 to 4:2:2 (downsampling).
Color Space Converter: This block converts Y´CbCr to RGB colour space or RGB to Y´CbCr colour space as required. There can be two situations when it can be used.
• When the video transmission is from digital camera to the LCD, and the digital camera outputs Y´CbCr 4:2:2 data.
• When video transmission is from the video decoder to LCD
Video Scaler: In case resolutions of the input and output device are different, this block up/down scales the input resolution to meet the output resolution.
Deinterlacer: This block separates the intermeshed odd and even fields of the NTSC/PAL frames output by the video decoder, into a combined, sequential de-interlaced frame, in order to display on LCD.
SDRAM Controller: Processed pixels are be buffered in memory before transmitting to the output device.
Write/Read DMA: Using DMA enables fast data transfers from peripheral to peripheral.
LCD Interface: This block outputs synchronized RGB x:x:x video data to an LCD.
Video Encoder Interface: This block outputs synchronized Y´CbCr 4:2:2 video (as per recommendation 601/656) to a video encoder like ADV 7390.
I/O formats
In order to drive the peripherals supported by the design, standard Y´CbCr 4:2:2 and RGB video in different color depths are supported. A description of the requirements of each interface is given below:
• Camera interface: Y´Cbcr 4:2:2 or RGB x:x:x data input/output where x:x:x might be 2:4:2, 5:6:5, 5:5:5 or 4:4:4
• Video decoder interface: Y´CbCr 4:2:2 input/output as per recommendation 601/656.
• LCD interface: RGB x:x:x input/output where x:x:x might be 4:4:4, 5:5:5, 5:6:5, 6:6:6 or 8:8:8
• Video encoder interface: Y´CbCr 4:2:2 input/output as per recommendation 601/656. Core descriptions
• LCD Interface
This module takes unformatted (without synchronization information) 24-bit RGB video data as input and formats them into frames comprising of separate 8-bit R, G and B outputs along with horizontal and vertical synchronization signals, which can be sent to an LCD controller/panel for display. The RGB formats supported are RGB 4:4:4, RGB 5:5:5, RGB 5:6:5, RGB 6:6:6 and RGB 8:8:8. The display size and pixel clock frequency are programmable. Polarities of data enable, frame clock and line clock can also be programmed. The interface supports progressive type of displays.
Here, the slave register block contains programmable control registers, which are configured prior to start of operation through the Slave Register interface. The FIFO stores the incoming pixels from the Pixel Input interface when the valid signal is high. The Timing Generator controls read access to the FIFO using values programmed in the control registers of the slave register block and also provides pixel clock, data enable and synchronization signals to the LCD.
• Camera Interface
Pre-processed frames from a camera/image sensor comprising of 10-bit Y?CbCr 4:2:2 or RGB video data along with vertical and horizontal synchronization signals, can be connected as input to this module. The interface decodes these incoming frames and outputs 16-bit video data only in a continuous stream (without synchronization/blanking information) in the same format for further processing by a downstream device. Specific RGB formats supported are RGB 2:4:2, RGB 5:6:5, RGB 5:5:5 and RGB 4:4:4.The vertical and horizontal resolutions as well as the frame and line clock polarities can be programmed by the user.
Here, the slave register block contains programmable control registers, which are configured prior to start of operation through the Register Slave interface. The FIFO stores the incoming pixels from the Camera interface, which are read out to the Pixel Output interface. The Capture Control block decodes the incoming sync signals and generates FIFO write access when the data bus has valid pixel data. Pixels are read from the FIFO when the ready signal is high at the Pixel Output interface. The valid signal at this interface indicates valid data on the output data bus. Soi and eoi lines indicate that the first and last data of a picture frame are present on the data bus.
• Video Decoder Interface
This module accepts 10-bit Standard Definition TV frames (digitized PAL/NTSC) in ITU-R BT.656 / BT.601 formats from a video decoder like ADV7180 and outputs 10-bit video data only in a continuous stream, stripped of blanking and synchronization information. The user can program the frame and line clock polarities.
Here, the slave register block contains programmable control registers, which are configured prior to start of operation through the Register Slave interface. The FIFO stores the incoming pixels from the Video Decoder interface, which are read out to the Pixel Output interface. The Capture Control block decodes the incoming sync signals and generates FIFO write access when the data bus has valid pixel data. Pixels are read from the FIFO when the ready signal is high at the Pixel Output interface. The valid signal at this interface indicates valid data on the output data bus. Soi and eoi lines indicate that the first and last data of a picture frame are present on the data bus. The field signal indicates whether the pixels on the data bus belong to the first or second field of the interlaced frame.
• Video Encoder Interface
This module takes as input 10-bit unformatted Y?CbCr 4:2:2 NTSC/PAL video and formats them into frames comprising of 10-bit Y?CbCr 4:2:2 video output along with horizontal and vertical synchronization signals in ITU-R BT.601 / BT.656 format. The output of the interface can be connected to a video encoder like ADV 7390. The user can program the frame and line clock polarities. Interlace scanned signals are supported by the interface.
Here, the slave register block contains programmable control registers, which are configured prior to start of operation through the Register Slave interface. The FIFO stores the incoming pixels from the Pixel Input interface when the valid signal is high. The Timing Generator controls read access to the FIFO using values programmed in the control registers of the slave register block and also provides pixel clock, data enable and synchronization signals to the Video Encoder.
• Chroma Resampler
This block upsamples or downsamples the chrominance components of images e.g. from Y´CbCr 4:2:2 to 4:4:4 (up sampling) or Y´CbCr 4:4:4 to 4:2:2 (down sampling).
• Color Space Converter
RGB to Y´CbCr or Y´CbCr to RGB color space conversion can be performed with this module.
• Video Scaler
This module can upscale the input resolution by any value from 1 to 4 or downscale by any value from 1 to 16. Upscaling is accomplished by pixel duplication while downscaling is accomplished by pixel dropping. Upto a maximum of 4096*4096 input resolution is supported.
Here, the register slave block contains the control registers for the scale values in the horizontal and vertical direction. Two synchronous FIFOs are used to store the input and scaled output video. The vertical scaling block scales the incoming image in vertical direction and stores in the DPRAM line buffers. The vertically scaled image is then passed on to the horizontal scaling block for scaling in the horizontal direction and stored in the output FIFO.
• DeInterlacer
Deinterlacing converts input interlaced (NTSC / PAL) video into a non-interlaced, sequential form suitable for modern display technologies such as LCDs.
Here, interlaced frame comprising of 8-bit pixels are input through the Pixel In interface to the Pixel In logic when the ready signal is high. The Pixel In Logic converts it to 32-bit and forwards to the Memory Interface Logic for writing to memory. The Memory Interface Logic takes care of write address generation and read and write control signal generation. The De-Interlace Control block then generates read address and performs deinterlacing by the weave method. The de-interlaced video is passed onto the Pixel Out Logic and presented on the Pixel Out interface along with the valid signal.
• SDRAM Controller
This module is an interface to a Single Data Rate SDRAM and features configurable timing parameters (CAS latency, tRP, tRCD and tREFC), mode register configuration and 64Mbit or 128Mbit SDRAM size configuration. 2 or 4 banks per device are supported which can be configured. The controller can perform Sequential Read/Write burst operations with Burst Length of 1, 2, 4, 8 or Full Page. Commands supported for SDRAM Operation are Normal Operation (Read/Write), Refresh, Precharge and Load Mode Register. An Auto Refresh with a programmable Refresh Counter is available. A simple DMA interface is featured for easy integration in any application.
Here, the Control Register block implements control registers for correct operation. The counters block implements different counters like Burst Counter, CAS Latency Counter, Precharge Counter, RCD Counter and Refresh Counter. On getting the grant, the DMA interface sends data enter to the Data Path block, which passes it on to the SDRAM with control inputs from the Command Generator block. The Command Generator block also sends commands to the SDRAM for load mode register, read, write, precharge and refresh operations using the values configured in the Counters block.
